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Our observations deal with what impact interconnect power has and how SSA impacts interconnect power. We use a low power high-level synthesis tool, called SCALP [10], to obtain RTL circuits and power consumption of controllers/datapaths, aided by our interconnect power estimation methods detailed in Section III. SCALP is interconnect-unaware. Considering memory design a separate issue from interconnect power optimization, we do not use any memory modules in the benchmarks. Instead, we use registers as storage units.


Lin Zhong 2003-10-11