Next: Gating signals with SSA
Up: Experimental Results
Previous: Experimental Results
In Fig. 14, power reduction obtained as a result
of incorporating interconnect-awareness into high-level synthesis
for low power is shown. Interconnect-awareness is achieved by
taking RTL interconnect power into account and using the two
proposed metrics (see Section IV) to guide iterative
improvement. Note that no signal gating is performed in this case.
Compared with interconnect-unaware power-optimized (IUPO)
circuits, interconnect-aware power-optimized (IAPO) circuits
consume 22.3% less power on an average while incurring only 0.5%
area overhead. Compared with area-optimized (AO) circuits, power
is reduced by an average of 53.3% at an average area overhead of
Power reduction due to interconnect-awareness.