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Different output network topologies

Three output network topologies were introduced in Section III. If all the output data are sent to all the receivers without regard to whether they need the data or not, the MST output network will consume the least power and the fully dedicated the most. If interconnect SSA is suppressed using the proposed techniques, however, this will not always be true. Fig. 10 shows a DPU, colored black, sending data to two other DPUs, colored white, using different output network topologies. It also shows the optimal locations for gating signals with SSA as small triangles.
Figure 10: Different output network topologies for (a) one DPU sending data to two other DPUs: (b) MST, (c) fully dedicated, and (d) trunk-branches.
Suppose tri-state buffers are used so that the last useful value is remembered in the gated idle cycles. Let $\alpha_1$ denote the unit-length switched capacitance for data, say, for variables $v_1,...,v_n$, needed by the upper receiver, which is estimated as

\alpha_1 =\sum_{i=1}^{n-1}SC(v_i,v_{i+1})

where $SC(v_i,v_{i+1})$ is the unit-length switched capacitance in the wire when $v_i$ is followed by $v_{i+1}$. That for the lower receiver, $\alpha_2$, and that for all the output variables of the sender, $\alpha$, can be estimated in the same way. Assuming signal gating is performed at the optimal locations shown in Fig. 10, we can estimate the total wire switched capacitance for the output network implemented as follows: MST, $SC_{MST}$, fully dedicated, $SC_{FD}$, and trunk-branches, $SC_{TB}$, as


The above equations imply that


Therefore, when $(\alpha_1+\alpha_2)>\alpha$, we have $SC_{FD}>SC_{TB}>SC_{MST}$ and when $(\alpha_1+\alpha_2)<\alpha$, $SC_{FD}<SC_{TB}<SC_{MST}$. Since $(\alpha_1+\alpha_2)$ can be either larger or smaller than $\alpha$, none of these topologies is always better than the others in terms of power consumption. In this work, the trunk-branches topology is assumed due to its never-the-worst power consumption and the algorithmic simplicity for constructing it.
next up previous
Next: SSA in buffers Up: Reducing Spurious Switching Activity Previous: Overhead for gating
Lin Zhong 2003-10-11