Next: Overhead for gating
Up: Reducing Spurious Switching Activity
Previous: Signal gating with filler
When one idle cycle of part of a circuit is both preceded and
followed by an active cycle, setting its inputs to a filler value
in that idle cycle will save very limited or no energy at all. In
this case and other situations in which the consecutive idle
cycles are not long enough, instead of using a filler value, we
can use tri-state gating without letting its output voltage value
drift to cause any problem. In typical ASICs, a properly sized
tri-state buffer can easily hold its output for a few clock cycles
without causing a problem in the downstream circuit. Therefore,
before deciding which gating logic to use, we examine the schedule
for data transfers. In case a gating logic has to gate for more
than two consecutive cycles, filler value gating is used.
Otherwise, a tri-state buffer is used.