Analysis of Delay Caused by Bridging Faults in RLC Interconnects
an abstract by Quming Zhou

A bridging fault is an undesired connection between two or more signal lines which accounts for a large portion of manufacturing defects. A bridge fault may produce a logic error or an extra delay on the affected signal wire. Such effects depend on the impedance of the interconnect lines and surrounding packaging as well as on the value of the bridging resistance. Bridging resistance has been shown to vary across a wide range. New developments in process technology have lead to an increase in the occurrence of resistance bridges. Moreover, as more metal interconnected layers are stacked, more masking steps are associated with building interconnects than with devices. Hence, major defects are associated with interconnects. Simulation tools such as SPICE give the most accurate insight into the delay estimation but are computationally expensive.

Other sources of interference, mainly coupling capacitance and inductance, can further complicate the analysis of bridging faults. Capacitive and inductive effects from rapidly switching closed-spaced interconnect lines can degrade signal integrity and may possibly lead to incorrect wire signal values and device malfunctions.

In this paper, we address the importance of coupling capacitance and inductance for delay evaluation in the presence of resistive bridges. We present a complete analytical bridging fault model which incorporates all physical properties, including RLC characteristics, of interconnects and coupling capacitances between interconnects. The purpose is to provide an accurate resistive bridging fault model so that bridging faults can be treated as delay faults during test generation.